Low-noise bias reliability of AlInAs/GaInAs MODFETs with linearly graded low-temperature buffer layers grown on GaAs substrates

AlInAs/GaInAs MODEETs lattice-matched to InP have been shown to be reliable at low bias (V/sub ds/=0.75 to IV) for low-noise applications. Mean-times to failure (MTTF) from 10/sup 5/ to 10/sup 7/ hrs., based on various failure criteria, have been reported for lattice-matched FETs. To improve manufacturability of these FETs we have fabricated 0.1 /spl mu/m T-gate AlInAs/GaInAs MODFETs on mismatched GaAs substrates by the insertion of a compositionally linearly graded low-temperature buffer (LGLTB) layer. In this work, we demonstrate that such FETs show comparable reliability at low bias under high temperature operating life (HTOL) tests to FETs on InP. Although the LGLTB layer is highly defective, there is no indication that the low-bias reliability of these devices is compromised. Our AlInAs/GaInAs MODFETS, grown on GaAs, have an extrapolated MTTF, based on I/sub dss/ drift, exceeding 10/sup 6/ hours at a channel temperature of 125/spl deg/C.