Passivation of InP-based heterostructure bipolar transistors-relation to surface Fermi level

The effect of the surface Fermi level position on the dc characteristics of InP-base heterostructure bipolar transistors (HBTs) is examined. The Fermi level of an InP surface covered with silicon oxide was located at an energy position close to the conduction band minimum of InP. This implies formation of an electron accumulation layer at the interface, which acts as a surface leakage path. The HBT passivated with silicon-oxide film showed a huge excess base current and poor current gain. In contrast, the Fermi level position at the silicon-nitride/InP interface was found to be near the midgap, and no electron accumulation layer formed at the interface. The HBT passivated with silicon-nitride film showed excellent dc characteristics with a very small excess base current.