Self-heating enhanced HCI degradation in pLDMOSFETs

The interface trap generation under V
_gmax
HCI stresses in pLDMOSFETs has been studied using non-destructive multi-region direct-current current-voltage (MR-DCIV) technique. Several times larger MR-DCIV degradation per finger was observed for multi-finger devices. Folded-gate layout device suffered more self-heating induced degradation. Our study results reveal that those effects shared the similar trends and mechanism with NBTI degradation. The self-heating enhanced degradation in multi-finger devices was due to the higher temperature rise and less channel edge heat dissipation. The impact of device layout on the HCI degradation has also been investigated. Our results suggested that the unfolded device layout can reduce self-heating enhanced V
_gmax
HCI degradation.