Optimization of HV LDMOS devices accounting for packaging interaction

The sensitivity of HV RESURF LDMOS transistors to parasitic charging in molding compound is investigated in this work by incorporating the passivation and encapsulation layers in the TCAD setup and implementing the conductivity losses in the mold. The role played by field plates and multiple metal/poly-silicon floating rings on the overall RESURF are revisited by focusing on the breakdown voltage degradation under high-voltage, high-temperature stresses. The layout re-optimization of a Single- and a Triple-RESURF LDMOS device using only MET1 and poly-Si levels is presented to reach a stable breakdown voltage after HTRB stress.