Demonstration of a HV BCD technology with LV CMOS process

Conventional BCD and high voltage technologies are developed with extra masks and additional thermal drive-in process units included in existing LV platforms. The technology development is time-consuming and the turnaround time for the whole process takes longer. In this paper, a low cost solution with a set of layout design methodology is proposed to accomplish the embedded power BCD technology in the existing 5V CMOS process without any additional process steps.