CALLAS/OASIS: Combining Behavioral and Register-Transfer Synthesis Systems

While behavioral synthesis has still to prove its feasibility in an industrial environment, register-transfer level synthesis is already accepted. Especially, behavioral synthesis has to compete with state of the art register-transfer synthesis in terms of area and timing of the synthesized chips. We have performed several controlled benchmark experiments, using test examples and chip designs that range from 300 to 50,000 transistors. Our results demonstrate that behavioral synthesis can generate logic and layout with performance which is comparable to those produced from register-transfer descriptions provided by a designer.