A comparison of parallel systemc simulation approaches at RTL

This paper presents a holistic comparison of different parallel SystemC simulation approaches at the register transfer level (RTL). The effect of RTL modeling styles and simulation strategies on performance will be evaluated to show potentials and limitations of state of the art parallel simulation techniques on shared memory machines. Experiments show that the simulation performance strongly depends on the used simulation strategy with speedups in the range from 2.3 to 13.4 on a 16 core machine.