Image convolution on FPGAs: the implementation of a multi-FPGA FIFO structure

We present an implementation of a real time convolver, based on field programmable gate arrays (FPGAs) to perform the convolution operations. Main characteristics of the proposed approach are the usage of external memory to implement a FIFO buffer where incoming pixels are stored and the partitioning of the convolution matrix among several FPGAs, in order to allow data parallel computation and to increase the size of the convolution kernel.