Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.