Workload-dependent BTI analysis in a processor core at high level

This work presents a software tool that enables joint architecture simulation and estimation of ageing-induced timing drifts at register-transfer level (RTL). The objective is to enable design exploration of processor microarchitecture under ageing constraint. The tool makes the bridge between user application, micro-architecture design, PVT corner and device-level degradation model. The environment will aid design engineers to apply early software and architecture optimizations at RTL for a better power consumption, performance and failure rate tradeoff.