TAF-DPS Clock Generator and On-Chip Clock Distribution

Clock distribution is a critical task in modern chip design. In recent years, advances in CMOS technology have led to an exponential increase in chip complexity. The most characteristic feature of the clock network is the large capacitive loading that it presents to the clock source. During operation, the clock source is responsible for the charge and discharge of this large capacitance. Clock buffers are attached to the metal structure to form the local clock distribution network. The task of frequency synthesis on a functional clock is accomplished by those time average frequency-direct period synthesis (TAF-DPSs). The TAF-DPS outputs can all be made synchronous to each other since their inputs are synchronized by the standing wave oscillators (SWOs), resulting in zero skew (theoretically). The FPGA (field programmable logic array) emerged in the 1980s as an alternative to the programmable logic device and application-specific integrated circuits (ASICs).