Evaluation of residual stress caused by flip-chip bonding process using piezo-resistor embedded test element group chips

The stress of ICs caused by flip-chip bonding process is evaluated using piezo-resistor embedded test element group (TEG) chips. The TEG size is 9 × 9 mm
²
with 550 μm in thickness. After non-conductive film (NCF) coating, the TEG chip is connected to the substrate by flip-chip bonding. The stress inside the chip was obtained in each process of flip-chip bonding by measuring the change in piezo-resistance. After bonding, the compressive stress is high in the center of TEG chips and the stress was lower towards the corner. The stress at elevated temperatures up to 123 °C is also measured. The compressive stress decreases with increasing temperature. The comparison between NCF and under-fill (UF) materials is performed through the same process.