A controllable setup and propagation delay flip-flop design

A Controllable flip flop design for sequential synchronous systems is proposed. The flip-flop setup time and propagation delay is controlled with an additional setup time and delay control (SDC) input. With this SDC enable, it is possible to enhance the circuit timing performance when required. In this paper, it is shown that when the SDC input is enabled, the flip-flop setup time and Clk-Q propagation delay are reduced, and when the SDC control remains disabled, the flip-flop reduces its timing margin saving power. The proposed flip-flop is designed and characterized in a TSMC 28 nm bulk CMOS technology.