CMOS amplifier with self-correction offset for SerDes applications

In Serializer/Deserializer (SerDes) systems usually there is a mismatch between the devices used in the circuitry handling the two complimentary signals and the analog front-end equalizer (AFE) circuit. This introduces an unknown and relatively steady offset voltage into the differential signals, this offset affects the noise margin of the system. A design of self-correction offset amplifier based on a continuous-time closed loop is proposed for minimizing input voltage offset coming from different sources in the range from - 30 mV to + 30 mV. Simulation results showed offset correction at the amplifier output which allows proper operation in SerDes systems. The amplifier was designed in AMI 0.5 μm CMOS technology, for 6 mW of power consumption and 3.0 V supply.