An FPGA cost estimation technique for design space exploration (DSE)

Increasingly sophisticated algorithms are now being used in wireless communication systems to achieve higher data rates, improved spectrum utilization and lower power transmission. Owing to the ever increasing speed requirements, field programmable gate arrays (FPGAs) have become an attractive option for communication systems due to the flexibility and computational power they offer. In this paper we present a new technique to estimate FPGA implementation cost for a given algorithm at early stages of design space exploration (DSE). An analytical approach is devised that can be used for hardware cost estimation for other computationally intensive algorithms as well. The technique analyzes MATLAB source code, computes computational requirements and produces area and speed estimates based on user input and information from library of FPGA cores. The core library contains parameters, such as area, speed, latency, precision etc. of all the IP cores available to the developer. This technique effectively enables the designer to estimate the implementation cost at design stage.