Efficient Voltage Regulation for Microprocessor Cores Stacked in Vertical Voltage Domains

Due to exponential (Moores law) scaling of advanced CMOS technologies, the challenges associated with delivering power to performance and mobile computing systems are outpacing the capabilities of conventional voltage regulator (VR) topologies. To continue to scale throughput at constant power density, the level of parallelism in microprocessor architectures is expected to increase substantially. In this paper, we present a power conversion topology to provide independent multicore regulation in the 0.8-1.4 V range from a 12-V dc bus. The topology uses a multistage ladder converter to manage power delivery to digital circuits stacked in vertical voltage domains. This approach has several advantages with regard to systems efficiency as it allows a more moderate conversion ratio of the main dc-dc converter. Moreover, the parallel converter only needs to process a fraction of the power of each core as the current can be “recycled” by adjacent cores in the stack. We develop a dynamical model for a multiple-input, multiple-output control scheme that uses a simple integral-control law, augmented with fast voltage- and current-mode feedforward. Measurement results of a discrete prototype verify the control scheme and demonstrate the potential advantages in system efficiency but also emphasize the remaining challenges in meeting stringent VR dynamic response requirements.