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Fast eye diagram analysis for high-speed CMOS circuits | IEEE Conference Publication | IEEE Xplore

Fast eye diagram analysis for high-speed CMOS circuits


Abstract:

We present an efficient technique for analyzing eye diagrams of high speed CMOS circuits in the presence of non-idealities like noise and jitter. Our method involves geom...Show More

Abstract:

We present an efficient technique for analyzing eye diagrams of high speed CMOS circuits in the presence of non-idealities like noise and jitter. Our method involves geometric manipulations of the eye diagram topology to find area within the eye contours. We introduce random tree based simulations as an approach to computing the desired area. We typically show 20× speedup in generating the eye diagram as compared to the state-of-the-art Monte Carlo simulation based eye diagram analysis. For the same number of samples, Monte Carlo produces an eye diagram that is 8.51% smaller than the ideal eye diagram. We generate an eye diagram that is 53.52% smaller than the ideal eye, showing a 47% improvement in quality.
Date of Conference: 09-13 March 2015
Date Added to IEEE Xplore: 23 April 2015
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Conference Location: Grenoble, France

References

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