Abstract:
This paper experiments with a methodology for mapping the 8×8 row-column Inverse Discrete Cosine Transform on general-purpose Very Long Instruction Word architectures. By...Show MoreMetadata
Abstract:
This paper experiments with a methodology for mapping the 8×8 row-column Inverse Discrete Cosine Transform on general-purpose Very Long Instruction Word architectures. By exploiting the parallelism inherent in the algorithm, the results obtained indicate that such processors, using sufficiently advanced compilers, can provide satisfactory performance at low cost without need to resort to special-purpose hardware or time-consuming hand-tuning of codes.
Published in: 9th European Signal Processing Conference (EUSIPCO 1998)
Date of Conference: 08-11 September 1998
Date Added to IEEE Xplore: 23 April 2015
Print ISBN:978-960-7620-06-4
Conference Location: Rhodes, Greece