A new FPGA architecture for image processing: CYCLOP

This paper presents CYCLOP, a multi-FPGA board architecture designed to allow real-time implementation of low-level image processing algorithms. A set of such identical boards is to be integrated into a workstation. It offers the users different algorithm implementation possibilities, depending on the trade-off speed area desired: — for applications requiring high speed computation rates, the user will have to consider the possibility to partition his algorithm into several boards (pipeline processing); — another method, illustrated in this paper, will consist in iterating the different steps of the algorithm on a single board. In the latter case, we implement a two-dimensional filtering environment. It is built on a one-dimensional second order recursive filtering unit, whose coefficients can be loaded via the VME bus. We illustrate the filtering performances by an immediate application to the Deriche edge detection algorithm.