A 10-bit 20-MS/s asynchronous SAR ADC with controllable analog input voltage range and meta-stability detection circuit

A 10-bit 20-MS/s asynchronous SAR ADC, which has a controllable analog input voltage range and a meta-stability detection circuit, is proposed. The proposed SAR ADC with the area of 0.095 mm² is implemented using a 130-nm CMOS process with 1.2-V supply. The measured peak ENOBs for the full rail-to-rail ±1.2V (peak-to-peak) differential sinusoidal input signal is 9.56 bits. The FoM achieves 41 fJ/conversion-step.