Understanding DDR4 in pursuit of In-DRAM ECC

Continuous DRAM scaling exacerbates problems caused by faulty cells, which lead to lower yields and more frequent errors. In-DRAM ECC is regarded as one of the solutions to overcome these issues. The latest DDR4 SDRAM specification includes new features to further improve reliability, such as an ALERT_n pad, which can be used to report errors detected by a SECDED code in DRAM. This paper identifies the possibilities and challenges of implementing In-DRAM ECC on DDR4 SDRAM devices.