A 6bit 550Ms/s small area low power successive approximation ADC

This paper presents a new capacitor array architecture to achieve a 6 bit 550Ms/s energy-efficient SAR with 65nm CMOS, which also takes up smaller area than traditional SAR. The bypass logic is a key feature to speed up the SA algorithm. Dynamic logic is used in the critical path to accelerate the speed. The whole circuit is supplied with 1.2V voltage. Simulation results show that the SAR achieves ENOB of 5.72, power consumption of 3.12mW with sampling rate at 550Ms/s, input frequency at Nyquist frequency.