A gain cell based embedded DRAM with fully-restoring write-back scheme

In this paper, we present a hybrid 2T gain cell based embedded DRAM with body-voltage controlled technique. The memory bit-cell is composed of a high-V
TH
write transistor and a standard-V
TH
read transistor. The negative cell-body toggle signal couples up the data ‘1’ storage level after data write. It results in an enhanced data retention time. Moreover, the proposed technique exhibits much strong immunity on write disturbance since the subthreshold leakage through the write device is drastically reduced. Simulation results from a 64-kbit eDRAM implemented in a 130 nm triple-well logic CMOS technology demonstrate the effectiveness of the proposed embedded memory technique.