Designing low-VTh STT-RAM for write energy reduction in scaled technologies

This paper investigates the use of extremely low threshold voltage (V
_Th
) for the select transistor in STT-RAM cell. While doing so intuitively improves its write margin, the extra current can also result in an MTJ oxide breakdown in the selected cell, as well as higher leakage current in an unselected cell inducing a false write in it. We thus propose an all-digital write driver to bias the selected source and bit lines (SL/BL) properly in order to guarantee a successful write operation while avoiding the above drawbacks. The proposed driver can be programmed per die to track die-to-die variations for maximum dynamic and leakage write energy reduction. The paper also describes the methodology used to design the cell and driver. Simulations in a 32nm commercial process show that a low-V
_Th
NMOS select device provides 18X improvement in STT-RAM write-margin as compared to a conventional cell, while the proposed driver offers up to 37% reduction in write energy per bit as compared to a conventional write diver.