Implementation of simplified normalized cut graph partitioning algorithm on FPGA for image segmentation

Normalized cut based image segmentation has a variety of applications in the area of image compression, medical imaging, mapping and measurements. But, the computational complexity of conventional normalized cut algorithm based on generalized eigenvalue problem is high. In this study, we proposed a simplified normalized cut algorithm using graph partitioning method for image segmentation. The computational cost of this simplified method are relatively low and hence, it can be implemented on real time embedded system applications. We have implemented an FPGA based image segmentation system using the simplified normalized cut algorithm and tested it for malarial parasites detection. Verilog Hardware Description Language (Verilog HDL) is used to develop the system and implemented on FPGA Spartan-6 targeted device xc6slx16- 2csg324. The Simple-As-Possible (SAP) computer architecture is used to design the system. We think the proposed architecture can be useful for real time image segmentation.