A 650 MHz pipelined MAC for DSP applications using a new clocking strategy

A 8×8 bit multiplier and accumulator unit for high speed applications is presented in this paper. The multiplier architecture is directly derived from the Baugh and Wooley algorithm, with some modifications, to reduce area and latency while the accumulator section is distributed along the multiplier structure. In this way the accumulator's latency is hidden in the multiplier's one. A new clocking strategy has been used for the design of the four stages pipelined accumulator cell, based on a full adder with partial feedback. The unit is synthesized in a 0.7μm Ν well CMOS technology. A one phase dynamic logic (True Single Phase Clocking — TSPC) has been adopted and the transistors widths had been sized by using an optimization algorithm achieving a clock frequency of 650 MHz with a latency of 36 clock cycles.