Implementation of a European paging system receiver using CORDIC algorithm

ERMES is a new European paging standard. The data transmission speed is higher than in older systems, e. g. POCSAG, and advanced new features are implemented including intelligent battery saving operation and country roaming. The higher speed is achieved using the more elaborate modulation method 4-PAM/FM which makes the demodulator implementation much harder than in older 2-FSK based paging systems. The objective of this paper is to propose a novel ERMES signal demodulator structure utilising a complex digital phase-locked loop which is implemented using the CORDIC algorithm. Phase-locked loop demodulators have inherently better performance than the normally used discriminator type detectors. Implementation of those phase-locked loop structures using the CORDIC algorithm makes VLSI realizations very feasible.