Design and implementation of a digital down converter chip

The design and implementation of a CMOS ASIC containing a digital down converter and a channel equalizer for a digital array antenna system is presented. The chip performs nearly 342×10
⁶
MAC/s (multiply-accumulate/second) at an internal bit-rate of 51.6 MHz. The circuit is based on a highly flexible architecture with few full-custom bit-serial arithmetic units.