Synthesis of memory-based VLSI architectures for discrete wavelet transforms

We propose novel VLSI architectures for computing the Discrete Wavelet Transforms. The proposed architectures employ a memory-based approach. ROM lookup tables are used for the implementation of complex computational modules. Compared with known architectures that employ traditional hardware computational modules, the proposed architectures are faster and are area-efficient. The memory-based architecture is used to implement the block-based DWT with parallel I/O. The resulting architectures are area-efficient and have high throughput and low latency. These architectures are suitable for low-power single-chip implementations which are useful for DWT-based mobile/visual communication systems.