Error analysis of ultra-wideband hybrid analogue-to-digital conversion

The error analysis of ultra-wideband hybrid analogue-to-digital conversion (H-ADC), which combines time-interleaved ADC (TI-ADC) and multiple concurrent ADC (MC-ADC), is presented. To this end, an error model is introduced comprising quantisation, overflow saturation, DC-offset, gain error, time delay, and time jitter due to sample-and-hold (S&H) circuits and clock generator. The impact of the system parameters on H-ADC performance is investigated by analytic evaluation of the error model assuming an arbitrary FDM input spectrum. The versatility of the H-ADC approach is demonstrated by a challenging future application of satellite on-board processing [1]: 1GHz overall FDM bandwidth with 12MHz channel spacing.