Which is the Best 2-to-1 Line Multiplexer for Ultralow-Power Applications?

This paper first investigates the output waveforms of various 2:1 multiplexer (2:1 MUX) circuits in different CMOS (Complementary MOS) logic styles at deep-sub threshold/low-frequency region at 16-nm technology node. It further compares the average power dissipation (taking both dynamic and leakage power into consideration) of those 2:1 MUX circuits which offer reliable output waveform to find out the best CMOS logic style for ultralow-power applications. Finally, the multiplexer circuit dissipating the least average power is implemented using emerging CNFET technology to achieve even better results in terms of different design matrices such as average power dissipation, propagation delay, power-delay product (PDP) and energy-delay product (EDP). CMOS transmission gate (CMOSTG) based circuit is found to dissipate minimum average power among all the other working CMOS logic styles and Simulation results show that its CNFET based realization further improves the output waveform along with reduction in average power dissipation (by 2×), propagation delay (by 1.3×), PDP (by 2.6×) and EDP (by 3.5×) respectively at 130 mV compared to its CMOS counterpart.

I. Introduction

Due to device dimension scaling energy dissipation has improved with each new technology generation, because SoCs (system-on-chip) are integrating billions of devices on-chip, the energy expended per operation has become a critical issue in integrated circuits [1]. Subthreshold circuits can solve this issue. Circuits in subthreshold region use the supply voltage less than the threshold voltages of the transistors. They consume less energy and dissipate less leakage power than their higher voltage alternatives, at the cost of slow speed. Hence, subthreshold circuits are ideal for ultralow-power applications where speed is not a major concern such as micro-sensor networks and nodes [2] [3], radio frequency identification (RFID) [4], low-power digital signal processor (DSP) and microcontroller units (MCU) in portable devices like mobile phones for non-performances critical operations during standby time using UDVS (ultra dynamic voltage scaling technique) [5]. Another application of CMOS circuits in subthreshold region is in wristwatch (which operates at 1 Hz) since it does not require very high speed circuits and thus could sacrifice performance to lower power. Also the hearing -aid requires very low frequency clocks, and thus can be operated in subthreshold region. Hence, it is necessary to investigate those circuits that can work at deep subthreshold/low-frequency region without any malfunctioning. Multiplexers are the basic sub-circuit in many complex digital circuits used in the above mentioned applications. In view of the above this paper provides a guideline for the circuit designers, who can appropriately select a suitable CMOS logic style for 2: 1 MUX realization for ultralow-power applications. In this regard this paper first investigates 2: 1 MUX in 13 different CMOS logic styles in deep-subthreshold region and output waveform of each is observed and based on that, 6 reliable CMOS logic styles having good output waveform at the mentioned conditions are picked out. Then comparison of average power dissipation among 6 selected CMOS logic styles is done. Based on the results obtained the CMOS logic style dissipating the least average power is selected for further optimization using emerging CNFET technology and comparison of different design matrices including average power dissipation, propagation delay, PDP and EDP between CNFET based circuit with its CMOS counterpart has been carried out.