Performance evaluation of fine time synchronizers for WLANs

In this paper the performance and implementation cost of three different fine time synchronization algorithms have been evaluated for their use in WLANs. In order to evaluate the performance, the residual time offset after fine time synchronization have been calculated. A hardware structure has been proposed for each algorithm and some simplifications are added that reduce the hardware cost without performance reduction. A Virtex II FPGA device has been selected as a target technology for the implementation. The results indicate that a cross-correlation algorithm with only 28 coefficients achieves the lowest hardware cost with similar performance with respect to the others algorithms.