Worst-case execution time analysis for digital signal processors

We present ongoing work to develop a software tool for estimating worst-case execution times for real-time, embedded programs. The tool applies static analysis to executable machine-code programs. Currently we mainly aim at supporting the TSC-21020E Digital Signal Processor, but the tool is designed to be easy to adapt to other target processors as well. Contrary to most other WCET tools we attempt (whenever possible) automatic estimation of loop bounds. We also provide a rich assertion language, which can be used to set bounds on loops that the tool itself cannot bound.