Verifying external data memory interface for H.263 video DSP with memory simulator

In this paper, we present the simulator-based method to estimate the time required by the external data memory accesses in the H.263 video encoding. Different frame rates and picture resolutions are considered. The Video DSP structure considered here consists of several parallel on-chip DSP units and it is optimized for the H.263 video encoding. Execution time is coarsely divided between control/non-sequential processing, parallel processing, and external data memory traffic. To evaluate the performance in early design phase, one must find out the time required by each part. The memory simulator method described here gives an estimate of the time required by the external memory accesses. With this estimate, one can also make sure that the proposed partitioning between internal and external data memories is correct and the required memory bandwidth for the external data memory is not too high.