FPGA implementation of an efficient proportionate affine projection algorithm for echo cancellation

This paper presents a field-programmable gate array (FPGA) implementation of a low-complexity proportionate affine projection algorithm (PAPA), in the context of echo cancellation. The proposed algorithm results as a combination between the recently developed “memory”-improved PAPA (MIPAPA) and a dichotomous coordinate descent (DCD) method. The MIPAPA takes into account the “history” of the proportionate factors, which is not the case for the classical PAPAs. Moreover, it achieves a lower computational complexity due to a recursive implementation of the “proportionate history;” as a consequence, the matrix that has to be inverted within the MIPAPA has the time-shift property, which can also lower the complexity. Concerning this task, the DCD technique efficiently performs the matrix inversion, requiring only addition operations. The proposed hardware implementation scheme takes advantage of the algorithm's specific features. The overall performance of the proposed DCD-MIPAPA indicates that it can be a reliable choice for real-world echo cancellation scenarios.