Reconfigurable architecture of AVC/H.264 integer transform

The paper presents an original reconfigurable architecture of inverse integer transformation for H.264/AVC decoder. Proposed design can perform integer 4×4, 8×8 and Hadamard inverse transform including inverse quantization process as well. The design exploits pipelined architecture and supports FPGA devices. Simulation result indicates that proposed structure is characterized by low implementation cost and high efficiency. Final synthesis and test has been made for Xilinx Virtex family devices.