Serial LDPC decoding on a SIMD DSP using horizontal scheduling

In this paper we propose an efficient vectorized low density parity check (LDPC) decoding scheme based on the min-sum algorithm and the horizontal scheduling method. Also, the well known forward-backward algorithm, used in the check-node messages update, is improved. Results are presented for 32 and 16 bits logarithm likelihood ratio messages representation on a high performance and modern fixed point DSP. The single instruction multiple data (SIMD) feature was explored in the 16 bits case. Both regular and irregular codes are considered.