Neural core module for embedded intelligence

A multiplication unit is proposed that allows for an efficient computation of products of 32-, 16- and 8-bit fixed point numbers. In the latter two modes of operation, two resp. four multiplications are executed in parallel. The proposed unit implements multiplication according to the DIGILOG principle and is designed to operate on a 100 Mhz clock in a 0.8 mm CMOS technology. The design of the unit is motivated by the potential benefits to be gained from a digital platform that integrates the emulation and training of neural networks with pre-processing of the signals that they process. Efficient realization of the multiplication operation is a major requirement of such a device.