Dynamic-floating-gate design for output ESD protection in a 0.35-/spl mu/m CMOS cell library

A dynamic-floating-gate design is proposed to improve ESD robustness of the driving-current-programmable CMOS output buffers in a 0.35 /spl mu/m CMOS cell library. Through suitable design to dynamically float the gates of the output NMOS/PMOS which are originally unused in a 2 mA output buffer, the ND-mode (PS-mode) ESD level of the 2 mA output buffer can be improved from the original 1.5 kV (1.0 kV) up to greater than 8 kV.