CMOS circuit design of threshold gates with hysteresis

M-of-N threshold gates with hysteresis form a class of circuit elements that have important application in NULL Convention Logic/sup TM/, a novel asynchronous logic design methodology. General design guidelines for these M-of-N gates are presented using CMOS technology. Three types of circuit implementations are discussed: static, semi-static and dynamic. In addition, initialization techniques are presented for use in establishing a known initial state.