Strained Si nanowire GAA n-TFETs for low supply voltages

In this work we demonstrate strained Si nanowire array n-TFETs with gate all around (GAA) structure yielding ON-currents of 5μA/μm at supply voltage V
_dd
= 0.5V. Tilted implantation into NiSi2 with BF2 dopant has been used to form a highly doped pocket for the source to channel tunneling junction. Measurements at room temperature indicates sub-threshold slopes (SS) below 60mV/dec for I
_d
<;10
^-4
μA/μm at V
_ds
=0.1V. For the analog device performance transconductance g
_m
=10 μS/μm, transconductance efficiency g
_m
/Id = 23V
^-1
and the conductance g
_d
= 0.8μs/μm normalized to the gate width have been extracted under for V
_dd
=0.5V.