TFET/CMOS hybrid pseudo dual-port SRAM for scratchpad applications

A hybrid TFET/CMOS pseudo Dual-Port SRAM (DPSRAM) for embedded scratchpad applications is presented in this paper. The DPSRAM bit cell is designed using sub-32nm TFETs to minimize leakage and the periphery logic is designed in 28-nm FDSOI CMOS to minimize area at a high operating speed. The bit cell is sized under dynamic stability and static noise margin constraints down to 0.6V. The static noise margin analysis is performed in order to be able to support dynamic voltage-frequency scaling (DVFS). The designed DPSRAM has ultra low leakage current less than 5fA/bit and sufficient read/write stability margin larger than 80 mV at 0.6V. For voltages below IV write-assist techniques are used.