F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data

The demand for ultra-high speed transceivers continues to rise exponentially due to the insatiable demand for high-throughput interconnect. Standards between 25 and 32Gb/s are rapidly approaching maturity, and available products and IPs at these rates are iterating to push down power while extending channel-loss recovery limits. Predictably, specifications are now in early stages for extending per-lane bandwith to between 40 and 64Gb/s. Meeting these 25Gb/s+ targets, especially for long-reach applications, is stressing the capabilities of both the underlying circuitry and the communication channels, and has caused significant rethinking of the overall system and circuit architectures for these links. In particular, the debate about multi-level (PAM4) versus binary (PAM2) signaling and which path offers the best energy-efficiency/data-rate scalability has returned to the foreground. Similarly, the emergence of high-speed ADCs with sufficient resolution for link applications has driven renewed interest in DSP-based approaches, while other efforts have pushed more analog/mixed-signal link components to over 60Gb/s/lane. To further ensure low BER operations, sophisticated coding such as FEC is brought into the discussion. Even in the domain of optical communications, significant challenges related to the bandwidth capabilities of the optical devices as well as the back end processing are currently being addressed. In fact, some of the highest speed optical links are limited by the short electrical interconnect between the driver circuitry and the optical module itself. This forum presents state-of-the-art I/O techniques enabling such high line rates across both optical and electrical interfaces as well as a number of emerging standards such as 802.3bj, various flavors of CEI, and HMC (hybrid memory cube).