Data lane design for transmitter of 4.8Gbps serdes in 65nm CMOS

This paper presents a data lane circuit for transmitter of 4.8Gbps serdes in 65nm CMOS process. The data lane circuit mainly consists of 32:1 multiplexer (MUX) and equalizer. MUX adopts half-rate architecture and CMOS circuits to relax clock requirement and save power. The equalizer is a 4-tap feed forward equalizer (FFE) that can operate at two driving modes. Measurement shows that FFE can compensate over 7 dB channel loss at 4.8Gbps. And comparison of two modes is presented as design reference. The circuit's area is 230×350 μm
²
.