A dual channel 10-b pipelined ADC for Intelligent Transport System

This paper describes a 10 b 40 MS/s dual channel pipelined ADC that is suitable for Intelligent Transport System (ITS). For proper operation in severe environment of vehicle, a dual-channel ADC core shares a band-gap (BGR) and current reference circuits. Also, the internal signal range amplification method extends the error correction range of the ADC, and the LDO-referencing technique reduces the circuit complexity by eliminating reference drivers. A 10 b ADC is implemented in a 180 nm CMOS process and achieves 59.3 dB SNDR and 74.9 dB SFDR at Nyquist input. Measured DNL/INL are -0.17/0.22 LSB and ±0.25 LSB, respectively. ADC consumes 42.44 mW at 3.3 V/1.8 V supplies.