Improvement on ESD robustness of LDMOS by bulk and source interleaved dotting

Source and bulk layout style is investigated for the purpose of improving ESD performance of multi-fingered high-voltage (HV) LDMOS. The device with bulk and source interleaved dotting (BSDOT) is fabricated in a 0.5μm 24V CDMOS process. Its ESD characteristics are studied employing transmission line pulse (TLP) measurement. Compared to traditional gate grounded nLDMOS (GG-nLDMOS) with a total length of 400μm, the proposed device can effectively increase the secondary breakdown current (I
_t2
) from 2.43A to 5.55A without any extra chip area.