Efficient implementation of a complete multi-beam radar coherent-processing on a telecom SoC

The processing bottleneck of modern multi-beam radar coherent-processing consists of the beamforming processing, the Doppler filtering and of the pulse compression stage. Pulse compression is a popular and an important technique in radars, which is known to be computationally expensive, therefore it was mainly implemented on ASICs or FPGAs due to the real-time and power constraints of many radar applications. Recent advances in multicore DSP architectures allow better flexible processing, reaching higher computational capability, while keeping the power consumption low. In this paper, we present an efficient implementation of a complete radar coherent-processing in a single TI SoC of 10W power consumption. The main optimization focus was on the pulse compression stage, where we proposed a different implementation approach optimizing memory usage and optimally parallelizing the processing in a multicore fashion, resulting in dramatic efficiency gains over conventional implementations. Experiments are done using the TI 6678 EVM and the TI 66AK2H EVM. We were able to implement the whole radar coherent-processing of “16 beams, 24 Doppler filters, 16 phased-array sensors and 1024 range cases sampled at 5MHz”, in only 3.2 C66 cores, fitting easily a single TI SoC of 10W power consumption, making a breakthrough in radar digital designs.