A Fully Planarized 0.25 /spl mu/m CMOS Technology

In this paper, a 0.25 mum CMOS technology using trench gate structure is developed, and excellent short channel effect and device characteristics are obtained. Furthermore, the entire structure is fully planarized with shallow trench isolation (STI) [2]. and buried trench gate in both silicon substrate and STi regions. Because it is fully planarized, the structure is also highly suitable for further planarized multi-level metal interconnection approaches.