A 3.42 /spl mu/m/sup 2/ Flash Memory Cell Technology Conformable to a Sector Erase

This paper describes a 3.42 μ m2 memory cell technology for a simple stacked gate Flash Memory, based on a 0.6μ m CMOS process. A sector erase scheme which uses a negative gate voltage is proven to be effective in realizing a selective erase for each word line. Versatile techniques to suppress aggravate erase and program disturb phenomena due to the sector erase and discussed.