Process Integration for a 2ns Cycle/4ns Access 512K CMOS SRAM

Recent results for a 512Kb SRAM [1] demonstrated a 2ns cycle and 4ns access performance. Essential to achieving this high speed result was optimization of the design in an advanced 0.8μ m CMOS technology which integrates 0.5μ m Leff n and p devices and a fully planarized three-level metal system. The 12 mask CMOS technology also features self-aligned TiSi2 cladding of source/drain and poly and stacked contacts/vias with void-free tungsten-fill. This paper describes the technology, its importance in high speed design, and measured results for technology control and SRAM speed.